1. Field of the Invention
The present invention generally relates to a semiconductor device. More particularly, the present invention relates to a semiconductor device having a voltage down-converter.
2. Description of the Background Art
Recently, transistors for use in semiconductor devices are increasingly miniaturized in order to implement reduced costs, reduced power consumption and increased operation speed. A power supply potential must be reduced in order to ensure reliability of the miniaturized transistors.
A semiconductor device is a fundamental component that is used together with various components in various equipments. However, reduction in voltage has not been implemented for most other components that are used in equipments including a semiconductor device. In view of matching between a semiconductor device and other components, a semiconductor device using a miniaturized transistor must operate with an external power supply potential that is high enough to degrade reliability if it is directly applied to the transistor.
Therefore, a voltage down-converter is required. The voltage down-converter is mounted within the semiconductor device, and serves to down-convert a high external power supply potential to the level acceptable to the miniaturized transistor in terms of reliability.
FIG. 23 is a circuit diagram showing the structure of a conventional voltage down-converter 524.
Referring to FIG. 23, voltage down-converter 524 includes a reference potential generator 534 for outputting reference potentials VREF, VBGR, and a down-converting portion 536 for receiving reference potentials VREF, VBGR, down-converting an external power supply potential EXTVDD and outputting an internal power supply potential INTVDD. Internal power supply potential INTVDD is supplied to a load circuit 526. Reference potential generator 534 and down-converting portion 536 have the same structure as that of a reference potential generator 34E and a down-converting portion 36 described later. Therefore, description thereof will not be given herein. In the figure, a resistor R2A has the same resistance value as that of a resistor R2.
Down-converting portion 536 is a circuit for receiving an external power supply potential EXTVDD and generating a lower internal power supply potential INTVDD based on a reference potential VREF generated by reference potential generator 534. Internal power supply potential INTVDD is given by the following expression (1):
                    INTVDD        =                                            R5              +              R6                        R5                    *                      VREF            .                                              (        1        )            
Accordingly, internal power supply potential INTVDD varies with variation in reference potential VREF. In order to prevent this, a semiconductor device is designed so that reference potential VREF is less susceptible to the internal power supply potential, process variation, and temperature variation.
FIG. 23 shows a bandgap-type reference potential generator 534. A bandgap-type reference potential generator is also called a “bandgap voltage reference”, and is commonly used as a reference potential generator causing less variation in reference potential VREF.
Hereinafter, a voltage generated by the bandgap-type reference potential generator will be described. In general, a current flowing through a diode is given by the following expression (2), where Is is a saturation current, q is the amount of charges of electron, k is a Boltzmann's constant, T is an absolute temperature and Vbe is a base-emitter voltage:
                    I        =                  Is          ⁡                      (                                          ⅇ                                  qVbe                  kT                                            -              1                        )                                              (        2        )                                                          ⁢                  ≃                      Is            *                          ⅇ                              qVbe                kT                                      ⁢                                                  ⁢                                          (                                  ∵                                      Vbe                    ⪢                                          kT                      q                                                                      )                            .                                                                                                    From          ⁢                                          ⁢          the          ⁢                                          ⁢          expression          ⁢                                          ⁢                      (            2            )                          ,                  Vbe          =                                    kT              q                        *            ln            ⁢                                          I                Is                            .                                                          (        3        )                                Accordingly        ,                  in          ⁢                                          ⁢                      Fig            .                                                  ⁢            23                          ,                            (        4        )                                          Vbel          -          Vbe2                =                              kT            q                    ⁢                      (                                          ln                ⁢                                  I1                  Is                                            -                              ln                ⁢                                  I2                  Is                                                      )                                                                                                        ⁢                  =                                    kT              q                        *                                          ln                ⁡                                  (                                      n                    *                                          I1                      I2                                                        )                                            .                                                                                                                Provided            ⁢                                                  ⁢            that            ⁢                                                  ⁢                          V              ⁡                              (                W12                )                                              =                      V            ⁡                          (              W13              )                                      ,                  I1          =                      I2            .                                                  ⁢            Therefore                          ,                            (        5        )                                          Vbel          -          Vbe2                =                              kT            q                    *                                    ln              ⁡                              (                n                )                                      .                                                                              Moreover        ,                              since            ⁢                                                  ⁢            Vbe2                    =                                    VBGR              -                                                (                                      R1                    +                    R2                                    )                                ⁢                I2                ⁢                                                                  ⁢                and                ⁢                                                                  ⁢                Vbel                                      =                          VBGR              -              R2I1                                      ,                                                                      R2I1          +                                    (                              R1                +                R2                            )                        ⁢            I2                          =                              kT            q                    ⁢                      ln            ⁡                          (              n              )                                                                                                    R1R2          =                                    kT              q                        ⁢                          ln              ⁡                              (                n                )                                                    ,                  I1          =                      I2            =                                                                                kT                    q                                    ⁢                                      ln                    ⁡                                          (                      n                      )                                                                      R1                            .                                                          (        6        )                                          From          ⁢                                          ⁢          the          ⁢                                          ⁢          expression          ⁢                                          ⁢                      (            6            )                          ,                                                            VBGR        =                  R2I1          +          Vbe1                                    (        7        )                                                          ⁢                  =                      Vbe1            +                                          R2                R1                            *                              kT                q                            *                                                ln                  ⁡                                      (                    n                    )                                                  .                                                                                                        Therefore        ,                                                            VREF        =                              R3                          R3              +              R4                                ⁢          VBGR                                    (        8        )                                                          ⁢                  =                                    R3                              R3                +                R4                                      ⁢                                          (                                  Vbe1                  +                                                            R2                      R2                                        ·                                          kT                      q                                        ·                                          ln                      ⁡                                              (                        n                        )                                                                                            )                            .                                                                      
Note that the expression (5) is obtained on the assumption that V(W12)=V(W13). The reason for this is as follows: since transistors P1, P2 of the same size are used, the same current flows through transistors P1, P2. In this case, by using transistors N1, N2 of the same size, a differential amplifier 38E controls the gate of a transistor P6 so that V(W12)=V(W13).
Potentials VBGR, VREF generated by reference potential generator 534 in FIG. 23 are thus given by the above expressions (7), (8), respectively.
Reference potential VREF is adjusted by adjusting the resistance value of resistors R3, R4. The level of internal power supply potential INTVDD is thus adjusted.
Resistors R1, R2 are formed from the same material so as to have the same variation in characteristics and the same temperature dependency. Similarly, resistors R3, R4 are formed from the same material so as to have the same variation in characteristics and the same temperature dependency. Similarly, resistors R5, R6 are formed from the same material so as to have the same variation in characteristics and the same temperature dependency. In the figure, resistors R2, R2A have the same resistance value and are formed from the same material.
It is known that process variation is a factor that cannot be ignored for a threshold voltage Vth of a MOS (Metal Oxide Semiconductor) transistor. In contrast, as described in “Analog Integrated Circuit Design Technology for VLSI”, Vol. 2, P. R. Gray, R. G. Meyer, Baifukan Co., Ltd, p. 310, Vbe is approximately unique to a material such as silicon and has little variation. However, Vbe has temperature dependency of about −2 mV/° C. Accordingly, ∂VBGR/∂T=0 is achieved by determining the resistance value of resistors R1, R2 so as to satisfy the following expression (9):
                              R2          R1                =                              -                                                            ∂                  V                                ⁢                                                                  ⁢                be                                            ∂                T                                              *                                    q              k                        ÷                                          ln                ⁡                                  (                  n                  )                                            .                                                          (        9        )            
As a result, potential VBGR generated by bandgap-type reference potential generator 534 is less susceptible to power supply voltage, process variation and temperature.
Accordingly, reference potential VREF is also less susceptible to power supply voltage, process variation and temperature.
Thus, internal power'supply potential INTVDD can be generated without being significantly affected by power supply voltage, process variation and temperature.
Recently, reduction in power consumption is increasingly required for the semiconductor devices, and therefore reduction in current consumption in the standby period is a prime task in the industry. In the semiconductor devices such as static random access memory (SRAM) and dynamic random access memory (DRAM), the value of a semiconductor device is determined mainly based on how fast the semiconductor device can start operation such as read and write operations after it transitions from standby to active state.
However, the voltage down-converter must drive a huge load circuit. Therefore, quick start operation cannot be implemented if the voltage down-converter is not operated until the semiconductor device transitions to the active state (i.e., if the voltage down-converter is stopped while the semiconductor device is in the standby state for the purpose of power saving).
Accordingly, the voltage down-converter must be operated from the standby state of the semiconductor device. Current consumption of the voltage down-converter thus accounts for a large percentage of a standby current of the semiconductor device. It is a bias current Ibias flowing through the differential amplifier that accounts for a large percentage of current consumption of the voltage down-converter. The circuit is therefore designed so as to minimize bias current Ibias.
However, as described in “VLSI Memory Chip Design”, Kiyoo Ito, Springer-Verlag Telos, 2001. 4, pp. 297–298, reducing bias current Ibias degrades responsiveness of the differential amplifier, thereby causing increase in voltage drop.
FIG. 24 illustrates a problematic voltage drop caused by a reduced bias current.
Referring to FIG. 24, the semiconductor device transitions from standby to active state at time t1. If bias current Ibias is reduced, responsiveness of the differential amplifier is degraded, whereby the potential on a node W17 drops with time delay. This increases the drop Vdrop of internal power supply potential INTVDD right after transition from standby to active state.
Although a certain level of voltage drop may be accepted, the drop Vdrop exceeding a prescribed allowable range would significantly affect the high speed operation of the semiconductor device.
In the structure of FIG. 23, the threshold voltage of an N-channel MOS transistor N3 in a differential amplifier 40 of down-converting portion 536 varies depending on process variation and temperature. Bias current Ibias of the differential amplifier is determined by Vgs−Vth of N-channel MOS transistor N3, that is, VBGR−Vthn. Even if the bandgap-type reference potential generator is designed so that potential VBGR does not vary as described before, variation in threshold voltage Vthn causes significant variation in bias current Ibias.
In other words, as threshold voltage Vthn is increased, bias current Ibias is reduced. This may excessively increase the voltage drop Vdrop.
On the other hand, as threshold voltage Vthn is reduced, bias current Ibias is increased. This may significantly increase the standby current.